The present invention relates to self-aligned semiconductor devices and a method for their manufacture. The invention is particularly application to self-aligned bipolar transistors. The present process may also relate to the manufacture of other self-aligned transistor components.
The fabrication of semiconductor transistor devices can be complex, requiring multiple steps which inherently incorporate any number of process limitations. These process limitations may ultimately affect the functioning of the transistor device. For example, the use of nonself-aligned processes results in multiple overlapping photo-patterning steps. The inherent inaccuracy resulting from these multiple photo-patterning process steps most often cannot be compensated for and may result in overlap between emitter and inactive base regions, which, in turn, can lower breakdown voltage. Alternatively, compensating for an overlap problem by allowing extra area between the active and inactive regions may create problems such as an undesirably high base resistance within the transistor.